The invention relates to a memory module having a memory cell with a first transistor and a capacitor. The capacitor is used for storing an information item and the first transistor is used for reading out and/or storing the information item from/to the capacitor. A first terminal of the first transistor is connected to a bit line.
Memory modules have a matrix of memory cells that are disposed in a form of rows and columns. The memory cells can be addressed via word lines and bit lines. The reading of data from the memory cells or the writing of data to the memory cells is carried out by the activation of the corresponding word line and of the corresponding bit line.
Known memory cells, such as e.g. of the DRAM type, usually have a transistor connected to a capacitor. In this case, a first terminal of the transistor is connected to a bit line and a second terminal of the transistor is connected to an electrode of the capacitor. The control terminal of the transistor is connected to a word line. By applying a suitable voltage to the word line the transistor is turned on and the charge stored in the capacitor is conducted via the bit line to an amplifier circuit. A central problem in known DRAM variants relates to in providing a sufficiently large capacitance of the capacitor. The size of the capacitors is continually being reduced through the increasing miniaturization of the memory modules. The decrease in size results in that the capacitance of the capacitor is also reduced. An amplifier circuit which evaluates the stored charge in the capacitor requires, for reliable functioning, a sufficiently large voltage change on the bit line during the read-out of the charge of the capacitor. The ratio of the storage capacitance to the bit time capacitance is crucial in determining the signal level that is established on the bit line during the read-out of the information from the capacitor. Therefore, the charge capacitance of the capacitor must not fall below a minimum magnitude.
It is accordingly an object of the invention to provide a memory module having a memory cell and a method for fabricating the memory module that overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, which has a relatively large charge capacitance.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory module. The memory module contains a voltage potential terminal for a voltage potential, a bit line, a first word line, a second word line, and a memory cell. The memory cell has a first transistor, a second transistor, a third transistor, and a capacitor with a first electrode and a second electrode. The capacitor is used for storing an information item and the first transistor is used for reading out or storing the information item from/to the capacitor. The first transistor has a first terminal connected to the bit line, a control terminal connected to the first word line, and a second terminal. The second transistor has a first terminal connected to the second terminal of the first transistor, a second terminal connected to the voltage potential terminal, and a control terminal connected to the first electrode of the capacitor. The third transistor has a first terminal connected to the first terminal of the second transistor, a second terminal connected to the first electrode of the capacitor, and a control terminal connected to the second word line.
One advantage of the invention is that the charge of the capacitor of the memory cell is used for switching a transistor that connects the bit line to a voltage potential. In this way, a small charge capacitance of the memory cell suffices to switch the transistor into an on state. The charge state of the memory cell is evaluated on the basis of the voltage potential. It is thus ensured that a sense amplifier receives a sufficiently large signal. Since the transistor is disposed near the capacitor of the memory cell, the charge capacitance stored in the memory cell is not impaired by long line paths. Consequently, the capacitor can be made relatively small and the charge capacitance of the storage capacitor can nevertheless still be reliably evaluated.
Preferably, a third transistor is provided, which enables an electrically conductive connection to the capacitor. The use of the third transistor results in that the capacitor can be charged.
Preferably, the transistors and the capacitor are introduced in a trench of a substrate. The substrate is produced from a semiconductor material for example. The configuration of the transistors and of the capacitor in a vertical trench results in that only a small area requirement of the surface of the substrate is needed to form the memory cell. Consequently, the configuration according to the invention is suitable for a large integration density.
In one preferred embodiment, the first transistor is formed on the surface of the substrate. The construction of the trench is simplified in this way.
In a further preferred embodiment, the first transistor is also disposed in the trench. In this way, only a very small surface is required for the configuration of the memory cell.
In a further preferred embodiment, the first and second word lines are disposed at least partly in the trench. This additionally results in a saving of surface area of the substrate. A further increase in the integration density is made possible as a result.
Preferably, at least two transistors are disposed on opposite sidewalls of the trench. An efficient utilization of the area of the trench is achieved in this way. As a result, it is possible overall to form the trench structure with a smaller depth. The transistors have conduction channels formed outside of the trench in adjoining regions in the substrate.
Preferably, the capacitor is disposed in the bottommost region of the trench and the transistors used for driving the capacitor are formed such that they lie above the region. A simple construction of the trench structure is made possible in this way.
With the foregoing and other objects in view there is further provided, in accordance with the invention, a method for fabricating a memory module. The method includes the steps of providing a substrate, forming a trench in the substrate, forming a capacitor in a bottom region of the trench, and forming a first transistor above the capacitor in a first part of a side region of the trench and in a first adjoining region of the substrate. The first transistor has a control terminal connected to a first electrode of the capacitor, and a terminal connected to a voltage potential. A second transistor is formed above the first transistor in a second part of the side region of the trench and in a second adjoining region of the substrate. The second transistor has a control terminal functioning as a word line disposed in the trench. A bit line is applied to the substrate. The bit line is electrically conductively connected to a terminal of the second transistor.
In accordance with an added mode of the invention, there is the step of forming a third transistor in a further side region of the trench and in a third adjoining region of the substrate. The third transistor has a control terminal functioning as a further word line and is disposed in the trench.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a memory module having a memory cell and a method for fabricating the memory module, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.